Electrostatic discharge (ESD) is a common occurrence in everyday life. While walking along a carpeted floor in a dry, heated room, for example, enough static electricity is stored within the human body to provide quite a shocking experience when contact is make with another object. Such a contact allows the stored static electricity to suddenly discharge from the human body into the contacted object. While this sudden discharge of static electricity may be of no harm to human bodies, it can be very damaging to electronic devices which are sensitive to ESD.
When an electrostatically charged person or object touches, or comes within sufficient proximity to, an ESD sensitive device, there is a possibility that the electrostatic charge can be discharged through circuitry contained within the ESD sensitive device. Such an ESD event could cause damage to occur in the electronic device due to, for example, localized overheating. Localized overheating may particularly occur at the interfaces associated with the electronic device, since the interfaces are first to come into contact with the electrostatic discharge. Of particular interest, are those electronic devices that are implemented on an Integrated Circuit (IC).
The current trend in IC design is to reduce component dimensions to improve performance characteristics such as parasitic delay, operational speed, and cost. Those same dimension reductions, however, may also contribute to ESD sensitivity. In particular, reduced device dimensions including shortened channel lengths, thinner gate oxide layers, and shallower junction depths may contribute to increased ESD sensitivity of the IC.
Depending on the type of IC interface and mode of operation, several conventional approaches have been devised to help mitigate the effects of ESD events. The simplest approach perhaps, is a resistor/capacitor (RC) combination placed at every driver output and receiver input on the IC, where a series connected resistor limits peak current caused by the ESD event, and a shunt capacitor limits short-term voltage peaks caused by the ESD event. Although the RC combination is relatively inexpensive, it only limits voltage slew rate, not peak voltage, and produces low pass filter (LPF) distortion, which among other detriments, reduces the maximum data rate possible.
Another conventional approach taken to mitigate ESD event damage utilizes an RC control circuit to activate a shunt device during an ESD event so that current resulting from the ESD event may be “shunted” away from the protected circuit. The inability, however, of the control circuit to: adequately detect the presence of an ESD event; while also allowing sufficient time to “shunt” current away from the protected circuit during the ESD event, have created a need for an improvement in conventional ESD protection circuitry.
In particular, although increasing the time constant of the RC control circuit results in a longer amount of time that may be used to “shunt” current away from the protected circuit, it also results in an increase in the physical dimensions of the components used to implement the RC control circuit. The physical size of these components, however, precludes their use in IC applications because of the significant amount of die area required to realize such components. Thus, other design approaches should be considered that not only provide extended ESD event protection, but also conform to the current trend in IC design to decrease component dimensions.
An apparatus and method that addresses the aforementioned problems, as well as other related problems, are therefore desirable.